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HT1647A 6416 LCD Controller for I/O MCU
Technical Document
* FAQs * Application Note
Features
* Operating voltage: 2.7V~5.2V * Built-in 32kHz RC oscillator * External 32.768kHz crystal oscillator or 32kHz fre* Eight kinds of time base/WDT selection * Time base or WDT overflow output * R/W address auto increment * Built-in buzzer driver (2kHz/4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * Provides VLCD pin to adjust LCD operating voltage * Provides three kinds of bias current programming * Control of TN-type, STN-type LCDs and ECB-type
quency source input
* Standby current: <1mA at 3V, <2mA at 5V * Internal resistor type: 1/5 bias or 1/4 bias, 1/16 duty * Two selectable LCD frame frequencies: 89Hz or
170Hz
* Max. 6416 patterns, 64 segments and 16 commons * Built-in bit-map display RAM: 1024 bits
(=6416 bits)
* Built-in internal resistor type bias generator * Six-wire interface (four data wires)
LCDs
* 100-pin QFP package and in chip form
Applications
* Leisure products * Games * Personal digital assistant * Cellular phone * Global positioning system * Consumer electronics
General Description
HT1647A is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 1024 patterns (64 segments and 16 commons). It also supports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1647A is a memory mapping and multi-function LCD controller. Since the HT1647A can control ECB-type (Electrically Controlled Birefringence) LCDs in addition to current TN-type (Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs. The software configuration feature of the HT1647A make it suitable for multiple LCD applications including LCD modules and display subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and the HT1647A.
Rev. 1.00
1
August 27, 2007
HT1647A
Block Diagram
OSCO OSCI CS RD WR DB0 DB3 VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r & T im e B a s e G e n e r a to r SEG 63 VLCD IR Q C o n tro l & T im in g C ir c u it D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it CO M 15 SEG0
N o te : C B W D C
S : C h ip s Z,BZ:To R,RD:W B0~D B3: O M 0~CO IR Q : T im e
e le c tio n n e o u tp u ts R IT E c lo c k , R E A D c lo c k D a ta b u s M 1 5 , S E G 0 ~ S E G 6 3 : L C D o u tp u ts b a s e o r W D T o v e r flo w o u tp u t
Pin Assignment
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE G4 G4 G4 G4 G4 G4 G5 G5 G5 G5 G5 G5 G5 G5 G5 G5 G6 G6 G6 G6 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
100 1
2 3
81 80
CS RD WR DB0 DB1 DB2 DB3 VSS OSCI OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 T4 NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
HT1647A 1 0 0 Q F P -A
30 31
51 50
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
43 42 41 40 39 38 37 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 36
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM 13 12 11 10 9 8 3 6 5 4 2 1 0 7 10 11 12 13 14 15
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HT1647A
Pad Assignment
SEG 41 1 SEG 40 SEG 39 SEG 38 SEG 37 99 SEG 36 SEG 35 SEG 34 SEG 33 SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 SEG 17
102 101 100
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77 76 75 74
SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 CO M 15 CO M 14 CO M 13 CO M 12 CO M 11 CO M 10 COM9 COM8
SEG 43 SEG 44 SEG 45 SEG 46 SEG 47 SEG 48 SEG 49 SEG 50 SEG 51 SEG 52 SEG 53 SEG 54 SEG 55 SEG 56 SEG 57 SEG 58 SEG 59 SEG 60 SEG 61 SEG 62 SEG 63 CS RD WR 9 8 7 6 5 4 3
2
73 72 71 70 69 68 67 66 65 64 (0 ,0 ) 63 62 61 60 59 58 57 56 55 54 53 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 DB0 DB1 DB2 DB3 VSS OP3 OP2 OSCI OSCO OP1 VDD VLCD IR Q BZ BZ T1 T2 T3 T4 COM0 46 COM1 47 COM2 48 COM3 49 COM4 50 COM5 51 COM6 52 COM7
10 11 12 13 14 15 16 17 18 19 20 21 22
Chip size: 3255 3050 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 X -1379.40 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 Y 1407.45 956.25 861.25 766.25 671.25 576.25 481.25 386.25 291.25 196.25 Pad No. 35 36 37 38 39 40 41 42 43 44 X -336.80 -233.40 -125.00 -28.00 77.60 172.60 295.20 408.80 522.40 636.00 Y -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 Pad No. 69 70 71 72 73 74 75 76 77 78 X 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 995.60
Unit: mm Y 593.85 688.85 783.85 878.85 973.85 1068.85 1163.85 1258.85 1353.85 1407.45
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HT1647A
Pad No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1512.50 -1441.90 -1441.90 -1441.90 -1240.80 -1145.80 -1040.20 -945.20 -842.00 -743.30 -637.70 -542.70 -437.10 Y 101.25 6.25 -88.75 -183.75 -278.75 -373.75 -468.75 -563.75 -658.75 -753.75 -848.75 -943.75 -1095.00 -1190.00 -1295.60 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 -1310.40 Pad No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 X 781.30 876.30 971.30 1066.30 1161.30 1256.30 1351.30 1446.30 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 1512.50 Y -1410.00 -1410.00 -1410.00 -1410.00 -1410.00 -1410.00 -1410.00 -1410.00 -949.55 -845.55 -759.55 -664.55 -569.55 -474.55 -379.55 -284.55 -166.15 -71.15 23.85 118.85 213.85 308.85 403.85 498.85 Pad No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 X 900.60 805.60 710.60 615.60 520.60 425.60 330.60 235.60 140.60 45.60 -49.40 -144.40 -239.40 -334.40 -429.40 -524.40 -619.40 -714.40 -809.40 -904.40 -999.40 -1094.40 -1189.40 -1284.40 Y 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45 1407.45
Pad Description
Pad No. Pad Name I/O Description Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1647A are disabled. The serial interface circuit is also reset. But if the CS is at a logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1647A are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT1647A are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1647A on the rising edge of the WR signal.
23
CS
I
24
RD
I
25 26~29 30 31 32 33 34
WR DB0~DB3 VSS OP1 OP2 OSCI OSCO
I
I/O Parallel data input/output with a pull-high resistor 3/4 I I I O Negative power supply for logic circuit, ground Used to select D3, D1 or D2, D0; OP1 input with pull-low resistor. OP1 pad is placed beside VDD pad. OP2 and OP3 are used to select two of four level gray scale; OP2 input with pull-high resistor. OP2 and OP3 pads are placed beside VSS pad. The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left open.
Rev. 1.00
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HT1647A
Pad No. 35 36 37 38 39, 40 41~44 45~60 Pad Name OP3 VDD VLCD IRQ BZ, BZ T1~T4 COM0~COM15 I/O I 3/4 I O O I O O Description OP2 and OP3 are used to select two of four level gray scale ; OP3 input with pull-high resistor. OP2 and OP3 pads are placed beside VSS pad. Positive power supply for logic circuit Power supply for LCD driver circuit Time base or Watchdog Timer overflow flag, NMOS open drain output. 2kHz or 4kHz frequency output pair (tristate output buffer) Not connected LCD common outputs LCD segment outputs
61~102, SEG0~SEG63 1~22
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current 5V IDD2 3V Operating Current 5V IDD11 3V Operating Current 5V IDD22 3V Operating Current 5V ISTB 3V Standby Current 5V VIL 3V Input Low Voltage 5V VIH 3V Input High Voltage 5V IOL1 3V BZ, BZ, IRQ Sink Current 5V VOL=0.3V VOL=0.5V DB0~DB3, WR, CS, RD 4.0 1.2 3 DB0~DB3, WR, CS, RD 0 2.4 Test Conditions VDD 3/4 3V Conditions 3/4 No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD OFF On-chip RC oscillator No load/LCD OFF Crystal oscillator No load, Power down mode Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 150 250 135 200 15 50 2 3 3/4 3/4 3/4 3/4 3/4 3/4 2.5 6 Max. 5.2 250 370 200 300 30 70 10 10 1 2 0.6 1.0 3 5 3/4 3/4
Ta=25C Unit V mA mA
mA
mA mA mA mA mA mA mA V V V V mA mA
Rev. 1.00
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August 27, 2007
HT1647A
Symbol Parameter Test Conditions VDD 3V BZ, BZ Source Current 5V IOL2 3V DB0~DB3 Sink Current 5V IOH2 3V DB0~DB3 Source Current 5V IOL3 3V LCD Common Sink Current 5V IOH3 3V LCD Common Source Current 5V IOL4 3V LCD Segment Sink Current 5V IOH4 3V LCD Segment Source Current 5V RPH1 3V Pull-high Resistor 5V RPH2 3V Pull-high Resistor 5V RPL 3V Pull-low Resistor 5V OP1 60 125 210 kW OP2, OP3 60 150 125 250 210 410 kW kW DB0~DB3, WR, CS, RD 60 150 125 250 210 410 kW kW Conditions VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V Min. -0.9 -2 1.2 3 -0.9 -2 80 180 -40 -90 50 120 -30 -70 150 Typ. -1.8 -4 2.5 6 -1.8 -4 160 360 -80 -180 100 240 -60 -140 250 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 410 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW
IOH1
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3V System Clock 5V 3V fSYS2 System Clock 5V 3V fSYS3 System Clock 5V fLCD1 3V LCD Frame Frequency 5V 3V fLCD2 LCD Frame Frequency 5V 3V fLCD3 tCOM LCD Frame Frequency 5V LCD Common Period 3/4 n: Number of COM External clock source Crystal oscillator On-chip RC oscillator 61/117 89/170 111/213 3/4 3/4 3/4 3/4 3/4 64 64 64 64 n/fLCD 3/4 3/4 3/4 3/4 3/4 External clock source Crystal oscillator On-chip RC oscillator 24 3/4 3/4 3/4 3/4 32 32.768 32.768 32 32 40 3/4 3/4 3/4 3/4 Conditions Min. 22 Typ. 32 Max. 40
Ta=25C Unit kHz kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz sec
fSYS1
61/117 89/170 111/213
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HT1647A
Symbol Parameter Test Conditions VDD 3V fCLK1 4-Bit Data Clock (WR Pin) 5V 3V fCLK2 4-Bit Data Clock (RD Pin) 5V tCS 4-Bit Interface Reset Pulse Width (Figure 3) 3/4 3V tCLK Read mode WR, RD Input Pulse Width (Figure 1) Write mode 5V Read mode t r, t f Rise/Fall Time Serial Data Clock 3V Width (Figure 1) 5V Setup Time for DB to WR, RD Clock 3V Width (Figure 2) 5V Hold Time for DB to WR, RD Clock 3V Width (Figure 2) 5V Setup Time for CS to WR, RD Clock 3V Width (Figure 3) 5V Hold Time for CS to WR, RD Clock 3V Width (Figure 3) 5V 3/4 3.34 3/4 1.67 3/4 3/4 ms 6.67 CS Write mode Duty cycle 50% Duty cycle 50% Conditions Min. 3/4 3/4 3/4 3/4 3/4 3.34 Typ. 3/4 3/4 3/4 3/4 250 3/4 Max. 150 300 75 150 3/4 3/4 Unit kHz kHz kHz kHz ns ms
120
3/4
ns
tsu
3/4
3/4
120
3/4
ns
th
3/4
3/4
120
3/4
ns
tsu1
3/4
3/4
100
3/4
ns
th1
3/4
3/4
100
3/4
ns
tf
tr
V
W R,RD C lo c k
90% 50% 10%
DD
V A L ID DB 50% ts
u
DATA V th 50%
DD
tC
LK
tC
GND
LK
GND
W R,RD C lo c k
GND
Figure 1
tC
S
Figure 2
CS
50% ts
u1
V
DD
th
1
GND V
DD
W R,RD C lo c k
50% F IR S T C lo c k LAST C lo c k
GND
Figure 3
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HT1647A
Functional Description
System Oscillator The HT1647A system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The clock source may be from an on-chip RC oscillator (32kHz), a crystal oscillator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well. The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, thus serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency 000H COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 D0 or D1 D2 or D3 001H D0 or D1 D2 or D3 002H D0 or D1 D2 or D3 003H D0 or D1 D2 or D3 004H D0 or D1 D2 or D3 005H D0 or D1 D2 or D3 006H D0 or D1 D2 or D3 007H D0 or D1 D2 or D3 SEG0 008H D0 or D1 D2 or D3 009H D0 or D1 D2 or D3 00AH D0 or D1 D2 or D3 00BH D0 or D1 D2 or D3 00CH D0 or D1 D2 or D3 00DH D0 or D1 D2 or D3 00EH D0 or D1 D2 or D3 00FH D0 or D1 D2 or D3 SEG1 SEG2 --------------------------- SEG61 017H ------------------------------1EFH 016H ------------------------------1EEH 015H ------------------------------1EDH 014H ------------------------------1ECH 013H ------------------------------1EBH 012H ------------------------------1EAH 011H ------------------------------1E9H source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 32kHz clock source operation. At the initial system power on, the HT1647A is at the SYS DIS state.
OSCI OSCO C r y s ta l O s c illa to r 32768H z E x te r n a l C lo c k S o u r c e 32kH z O n - c h ip R C O s c illa to r 32kH z
S y s te m C lo c k
System Oscillator Configuration Display Memory - RAM Structure The static display RAM is organized into 5122 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. 1F0H D0 or D1 D2 or D3 1F1H D0 or D1 D2 or D3 1F2H D0 or D1 D2 or D3 1F3H D0 or D1 D2 or D3 1F4H D0 or D1 D2 or D3 1F5H D0 or D1 D2 or D3 1F6H D0 or D1 D2 or D3 1F7H D0 or D1 D2 or D3 SEG62 1F8H D0 or D1 D2 or D3 1F9H D0 or D1 D2 or D3 1FAH D0 or D1 D2 or D3 1FBH D0 or D1 D2 or D3 1FCH D0 or D1 D2 or D3 1FDH D0 or D1 D2 or D3 1FEH D0 or D1 D2 or D3 1FFH D0 or D1 D2 or D3 SEG63
010H ------------------------------1E8H
Note: One bit of RAM maps to LCDs one pixel and decide 2-level gray scale. RAM structure depends on OP1, OP2 and OP3 option. Rev. 1.00 8 August 27, 2007
HT1647A
Write Data Mapping to RAM for Pad Option Pad Option OP1 OP2 0 0 1 1 0 0 1 1 OP3 0 1 0 1 0 1 0 1 Level Selected Level2 (1,0) Level3 (0,1) Level4 (0,0) Level3 (0,1) Level2 (1,0) Level1 (1,1) Level4 (0,0) Level1 (1,1) Level3 (0,1) Level2 (1,0) Level4 (0,0) Level2 (1,0) Level3 (0,1) Level1 (1,1) Level4 (0,0) Level1 (1,1) RAM Data 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Level1 and Level4 are not used Level1 and Level2 are not used Level3 and Level4 are not used Level2 and Level3 are not used Level1 and Level4 are not used Level1 and Level3 are not used Level2 and Level4 are not used Level2 and Level3 are not used
0 (Select D2 and D0)
1 (Select D3 and D1)
Note: OP1 is used to select D3, D1 or D2, D0. OP2 and OP3 are used to select two of four level gray scale.
Gray Scale Level Decision HT1647A uses PWM technique to provide gray scale display and only two of four level gray scale can be displayed simultaneously by setting OP1~OP3 pads. OP1 is used to select D3, D1 or D2, D0 and OP2 and OP3 are used to select two of four level gray scale. The four level gray scale are defined below table RAM Data Defined Gray Scale Level. MCU write two bits data and only one bit data is written to internal display RAM. The OP1~OP3 pads setting is shown as following table Write Data Mapping to RAM for Pad Option. RAM Data Code (D3, D2) or (D1, D0) (1, 1) (1, 0) (0, 1) (0, 0) Choice Gray Scale Level Level 1 Level 2 Level 3 Level 4
Gray Scale Display If the user choose 89Hz frame frequency, a max. of 24 sections can be programmed to suit a satisfactory gray scale in every level. Similarly, if the user choose 170Hz frame frequency, a max. of 13 sections can be programmed to suit a satisfactory gray scale in every level. HT1647A provides 5-bit PWM data to control the length of the section. In other words, a max. Of 24 gray scales are generated by 5-bit binary PWM data. At FRAME 89Hz mode, the HT1647A only provides a max. of 24 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When 5 bits binary code value is more than 23, the PWM control circuit uniformly regards 23. To increase PWM data indicates to increase the length of the active segment signal. The varied length of the active segment signal displays varied gray scale in TN-type, STN-type LCDs (refer to table 1). Similarly, it displays varied color in ECB-type LCDs. The color display is derived from ECB-type LCD specification. At FRAME 170Hz mode, the HT1647A only provides a max. of 13 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When the 5 bits binary code value is more than 12, the PWM control circuit uniformly regards 12. The user must appoint four kinds of PWM data to four kinds of different gray scale level by commanding PWM data (refer to table 2).
RAM Data Defined Gray Scale Level Frame Frequency HT1647A provides two kinds of frame frequency option by command code; 89Hz and 170Hz respectively. FRAME 89Hz provides 89Hz frame frequency and active segment signal width can be divided into 24 sections concurrently. FRAME 170Hz provides 170Hz frame frequency and active segment signal width can be divided into 13 sections concurrently. The 24 sections display a particularly gray scale more than the 13 sections by PWM data. The default is FRAME 89Hz. Rev. 1.00 9
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HT1647A
Name FRAME 170Hz FRAME 89Hz Command Code X100-0001-1000-XXXX X100-0001-1101-XXXX Function Select 170Hz frame frequency and active segment signal width can be divided into 13 sections Select 89Hz frame frequency and active segment signal width can be divided into 24 sections
Frame Frequency Selection Command Code
Relationship Table between PWM Data and Gray Scale
V a lu e 0 1 2 3 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 4 5 b its P W M B4 B3 B2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 d a ta B1 B0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 (O N PW M w id th ) G r a y S c a le 0 (0 /2 3 ) 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 1 (2 3 /2 3 ) 1 (2 4 /2 3 ) 1 1 1 1 1 1 1 1 1 1 2 2 2 V a lu e 0 1 2 3 4 5 6 7 9 10 11 12 13 8 5 b its P W M B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 d a ta B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PW M w id 0 (0 /1 1 /1 2 2 /1 2 3 /1 2 4 /1 2 5 /1 2 6 /1 2 7 /1 2 8 /1 2 9 /1 2 0 /1 2 1 /1 2 (1 2 /1 (1 3 /1 G r a y S c a le
(O N
th ) 2)
1
1 1 1
2) 2)
31
1 1
1
1
1
1 (3 1 /1 2 )
Table 2: FRAME 170Hz Mode Note: The varied PWM data displays various gray scale in TN-type, STN-type LCDs. The color display derives from ECB-type LCDs specification.
31
1 1
1
1
1
1 (3 1 /2 3 )
Table 1: FRAME 89Hz Mode Name GRS LEVEL 1 GRS LEVEL 2 GRS LEVEL 3 GRS LEVEL 4 Command Code X100-001 B4-B3 B2 B1 B0-XXXX X100-010 B4-B3 B2 B1 B0-XXXX X100-011 B4-B3 B2 B1 B0-XXXX X100-100 B4-B3 B2 B1 B0-XXXX Function Set PWM data in gray scale level 1 Set PWM data in gray scale level 2 Set PWM data in gray scale level 3 Set PWM data in gray scale level 4
Four Kinds of Gray Scale Level Command Code
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HT1647A
V COM V
16
LCD
1
2
16
1
2
V1 V2 V3 V4
SS
W V SEG V
LCD
W'
V1 V2 V3 V4
SS
W' V 3 /5 V CO M ~SEG 1 /5 V -1 /5 V -3 /5 V -V
LCD LCD LCD LCD LCD LCD
W
ON 1 fr N o t e : " W '" R e a l a c t iv e s e g m e n t s ig n a l w " W " M a x . a c tiv e s e g m e n t s ig n a l w P W M ( O N w id t h ) : W '/ W , 0 W '/ W am id id 1
ON OFF e th ( a d ju s ta b le w id th b y P W M th ( r e fe r to ta b le 1 & ta b e l 2 )
d a ta )
Example of Waveform (B Type) in 1/5 Bias, 1/16 Duty Cycle Drive
Time Base and Watchdog Timer - WDT The time base generator and WDT share the same counter which is divided by 256. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out ocT im e B a s e C lo c k S o u r c e /2 5 6 V CLR T im e r
DD
curs, the IRQ pin will remain at a logic low level until the CLR WDT or the IRQ DIS command is issued. If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed.
T IM E R E N /D IS IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT /4
CLR
W DT
Time Base and WDT Configurations
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HT1647A
Buzzer Tone Output A simple tone generator is implemented in the HT1647A. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable that can turn on the tone output. The TONE 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. Name Command Code Function tion command, a bias current selection command, a gray scale level selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100
TONE X100-0000-1000-XXXX Turn-off tone output OFF Turn-on tone output, TONE X100-0001-0000-XXXX tone frequency is 4K 4kHz Turn-on tone output, TONE X100-0001-0001-XXXX tone frequency is 2K 2kHz Buzzer Tone Output Command Code Command Format The HT1647A can be configured by software setting. There are two mode commands to configure the HT1647A resource and to transfer the LCD display data. The configuration mode of the HT1647A is called command mode, and its command mode ID is 100. The command mode consists of a system configuration command, a system frequency selection command, an LCD configuration command, a tone frequency selec-
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will also be reset. The CS pin returns to 0, so a new operation mode ID should be issued first. Bias Generator The HT1647A bias voltage belongs to internal resistor type. It provides two kinds of bias option named 1/5 bias and 1/4 bias respectively. It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs. It also provides three kinds of bias current option by programming to suitably drive an LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during On condition when the LCD is normally displayed. The following are the reference value table. Middle Bias Current 100mA 125mA Small Bias Current 40mA 50mA
VLCD 4V 4V
Bias 1/5 1/4
Large Bias Current 300mA 375mA
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HT1647A
VDD * VLCD R V1 R V2 R V3 R R V4 R R VSS 1 /4 b ia s VSS 1 /5 b ia s V4 *V
LCD
VDD VR * VLCD R V1 V2 R V3 R *V
LCD
VR
* T h e v o lta g e a p p lie d to V L C D p in m u s t b e lo w e r th a n V D D * A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W 2 0 %
Internal Resistor Type Bias Generator Configurations
Interfacing Only six lines are required to interface with the HT1647A. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1647A. If the CS pin is set to 1, the data and command issued between the host controller and the HT1647A are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1647A. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all clocked into the HT1647A on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1647A. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1647A.
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D a ta (M A + 1 5 ) D a ta (M A + 1 4 ) D a ta (M A + 1 3 ) D a ta (M A + 1 2 ) D a ta (M A + 1 1 ) D a ta (M A + 1 0 ) ( S u c c e s s iv e a d d r e s s r e a d in g ) D a ta (M A + 9 ) D a ta (M A + 8 ) D a ta (M A + 7 ) D a ta (M A + 6 ) D a ta (M A + 5 ) D a ta (M A + 4 ) D a ta (M A + 3 ) D a ta (M A + 2 ) D a ta (M A + 1 ) D a ta (M A ) M e m o ry A d d re s s (M A )
D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 5 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 4 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 3 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 2 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 1 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 0 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 8 ) D3 D2 D1 D0 D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 7 ) D3 D2 D1 D0
D a ta (M A + 6 ) D3 D2 D1 D0
D a ta (M A + 5 ) D3 D2 D1 D0
D a ta (M A + 4 ) D3 D2 D1 D0
D a ta (M A + 3 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 2 ) D3 D2 D1 D0
D3
D2
D1
D0
D a ta (M A + 1 ) D a ta (M A ) D3 D2 D1 D0 M e m o ry A3 A2 A1 A0
D3
D2
D1
D0
( S u c c e s s iv e a d d r e s s w r itin g )
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D0
D0
D0
D0
D a ta (M A + 9 )
A5
A7
A6
A4
A8
C o m m a n d ID 0
code
A d d re s s (M A ) A7 A6 A5 A4 1 0 1
A8
1
1
C o m m a n d ID
code
WRITE mode (command ID code : 1 0 1)
READ mode (command ID code : 1 1 0)
( S in g le a d d r e s s r e a d in g )
Timing Diagrams
D3
A3
A2
A1
A7
A6
A5
A8
C o m m a n d ID A8 1 1 0
code
A4
A d d re s s (M A ) A7 A6 A5 A4
A0
M e m o ry A3 A2 A1 A0
D2
D1
D0
D a ta (M A ) D3 D2 D1 D0
D a ta (M A ) M e m o ry
A d d re s s (M A ) 1 0 1
C o m m a n d ID
code
( S in g le a d d r e s s w r itin g )
Rev. 1.00
WR DB3 DB2 DB1 DB0
WR
CS
RD
DB3
DB2
DB1
DB0
CS
RD
14
A0
A3
A2
A1
August 27, 2007
HT1647A
D3
D2
D1
D0
HT1647A
READ-MODIFY-WRITE mode (command ID code : 1 0 1)
CS
WR
RD
DB3
A8
A7
A3
D3
D3
A8
A7
A3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
DB2
1
A6
A2
D2
D2
1
A6
A2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
DB1
0
A5
A1
D1
D1
0
A5
A1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
DB0
1 C o m m a n d ID code
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0 D a ta (M A )
1 C o m m a n d ID code
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0 D a ta (M A )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 6 )
D0 D a ta (M A + 6 )
( S in g le a d d r e s s a c c e s s in g )
( S u c c e s s iv e a d d r e s s a c c e s s in g )
Command mode (command ID code : 1 0 0)
CS
WR
RD
DB3
X
C8
C4
C0 X
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
DB2
1
C7
C3
X
1
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3 X
DB1
0
C6
C2
X
0
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2 X
DB0
0 C o m m a n d ID code
C5
C1 Com m and
X
0 C o m m a n d ID code
C5
C1 Com m and 1
X
C5
C1 Com m and 2
X
C5
C1 Com m and 3
X
C5
C1 Com m and 4
X
C5
C1 Com m and 5
X
C5
C1 X Com m and 6
( S in g le c o m m a n d )
( S u c c e s s iv e c o m m a n d )
Note: X stands for dont care
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HT1647A
Application Circuits
Host Controller with an HT1647A Display System
*
CS RD WR VDD *V R VLCD H T1647A BZ IR Q OSCI BZ CO M 0 ~ CO M 15 SEG 0~SEG 63 P ie z o
MCU *R
DB0~DB3
C lo c k O u t E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C
OSCO
* 1 /5 B ia s ( o r 1 /4 B ia s ) , 1 /1 6 D u ty LCD Panel
C ry s ta l 32768H z
*Note: The connection of IRQ and RD pin can be selected depending on the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW 20%. It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs. Adjust R (external pull high resistance) to fit users time base clock.
Instruction Set Summary
Name READ WRITE Command Code A8110-A7A6A5A4A3A2A1A0D3D2D1D0 A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D/C D D D C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn Off both system oscillator and LCD bias Yes generator Turn On system oscillator Turn Off LCD display Turn On LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn Off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage Turn on tone output, tone frequency output: 4kHz Turn on tone output, tone frequency output: 2kHz Yes Yes Yes Yes Def.
READ-MODIFYA8101-A7A6A5A4A3A2A1A0D3D2D1D0 WRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT TONE 4K TONE 2K X100-0000-0000-XXXX X100-0000-0001-XXXX X100-0000-0010-XXXX X100-0000-0011-XXXX X100-0000-0100-XXXX X100-0000-0101-XXXX X100-0000-0110-XXXX X100-0000-0111-XXXX X100-0000-1000-XXXX X100-0000-1101-XXXX X100-0000-1111-XXXX X100-0001-0000-XXXX X100-0001-0001-XXXX
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HT1647A
Name IRQ DIS IRQ EN RC 32K EXT (XTAL) LARGE BIAS MIDDLE BIAS SMALL BIAS BIAS 1/5 BIAS 1/4 FRAME 170Hz Command Code X100-0001-0010-XXXX X100-0001-0011-XXXX X100-0001-0100-XXXX X100-0001-0101-XXXX X100-0001-0110-XXXX X100-0001-0111-XXXX X100-0001-1000-XXXX X100-0001-1001-XXXX X100-0001-1010-XXXX X100-0001-1100-XXXX D/C C C C C C C C C C C Function Disable IRQ output Enable IRQ output System clock source, on-chip RC oscillator System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Large bias current option Middle bias current option Small bias current option LCD 1/5 bias option LCD 1/4 bias option Selects 170Hz frame frequency and active segment signal width can be divided into 13 sections Selects 89Hz frame frequency and active segment signal width can be divided into 24 Yes sections Sets PWM data in gray scale level 1 Sets PWM data in gray scale level 2 Sets PWM data in gray scale level 3 Sets PWM data in gray scale level 4 Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 64Hz The WDT time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode Yes Yes Yes Yes Yes Def. Yes
FRAME 89Hz GRS LEVEL1 GRS LEVEL2 GRS LEVEL3 GRS LEVEL4 F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note:
X100-0001-1101-XXXX X100-001 B4-B3 B2 B1 B0-XXXX X100-010 B4-B3 B2 B1 B0-XXXX X100-011 B4-B3 B2 B1 B0-XXXX X100-100 B4-B3 B2 B1 B0-XXXX X100-1010-0000-XXXX X100-1010-0001-XXXX X100-1010-0010-XXXX X100-1010-0011-XXXX X100-1010-0100-XXXX X100-1010-0101-XXXX X100-1010-0110-XXXX X100-1010-0111-XXXX X100-1111-1111-XXXX X100-1111-1110-XXXX
C C C C C C C C C C C C C C C
X stands for dont care A8~A0: RAM address D3~D0: RAM data B4~B0: PWM data D/C: Data/Command mode Def.: Power-on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The tone frequency source and the time base/WDT clock frequency source can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1647A after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the HT1647A.
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HT1647A
Package Information
100-pin QFP (1420) outline dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.80 13.90 24.80 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.00
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HT1647A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
19
August 27, 2007

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